LPFLLCMRE=0, LPFLLVLD=0, LK=0, LPFLLTREN=0, LPFLLEN=0, LPFLLERR=0, LPFLLCM=0, LPFLLSEL=0, LPFLLTRUP=0, LPFLLTRMLOCK=0
Low Power FLL Control Status Register
| LPFLLEN | LPFLL Enable 0 (0): LPFLL is disabled 1 (1): LPFLL is enabled |
| LPFLLTREN | LPFLL Trim Enable 0 (0): Disable trimming LPFLL to an reference clock source 1 (1): Enable trimming LPFLL to an reference clock source |
| LPFLLTRUP | LPFLL Trim Update 0 (0): Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value. 1 (1): Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication |
| LPFLLTRMLOCK | LPFLL Trim LOCK 0 (0): LPFLL not Locked 1 (1): LPFLL trimmed and Locked |
| LPFLLCM | LPFLL Clock Monitor 0 (0): LPFLL Clock Monitor is disabled 1 (1): LPFLL Clock Monitor is enabled |
| LPFLLCMRE | LPFLL Clock Monitor Reset Enable 0 (0): Clock Monitor generates interrupt when error detected 1 (1): Clock Monitor generates reset when error detected |
| LK | Lock Register 0 (0): Control Status Register can be written. 1 (1): Control Status Register cannot be written. |
| LPFLLVLD | LPFLL Valid 0 (0): LPFLL is not enabled or clock is not valid. 1 (1): LPFLL is enabled and output clock is valid. |
| LPFLLSEL | LPFLL Selected 0 (0): LPFLL is not the system clock source 1 (1): LPFLL is the system clock source |
| LPFLLERR | LPFLL Clock Error 0 (0): Error not detected with the LPFLL trimming. 1 (1): Error detected with the LPFLL trimming. |